1. Field of the Invention
The present invention generally relates to various semiconductor structures and more particularly to an improved structure that includes improved sub-collector areas that have non-planar surfaces.
2. Description of the Related Art
With mixed voltage interface (MVI) applications, the desire to have multiple MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices and multiple bipolar transistors in CMOS (Complementary Metal Oxide Semiconductor) and BiCMOS (Bipolar CMOS) technologies is common practice. It is also common practice in CMOS to have thin oxide, and dual oxide MOSFET devices to provide this capability. Additionally, in BiCMOS technology, both a high breakdown (HB) and high performance (HP) BJT (Bipolar Junction Transistor) (or HBT) device is desirable for mixed voltage applications that require both high voltage interfaces as well as performance requirements. The addition of multiple oxides and multiple transistors is achieved using additional process steps. These processes all add additional cost to the technology. As technologies become more advanced, the number of supported MOSFETs and bipolar devices increases. As a result, it is advantageous to provide both active and passive elements which can be achieved with less process expense, a reduced number of masks and less processing steps.
To continue to reduce cost, and maintain dimensional similitude, the vertical profiles of transistors are scaled (reduced in size) laterally and vertically. To lower costs, epitaxial regions are scaled in the vertical dimension. Additionally, with epitaxial elimination, sub-collectors are required to be implanted due to limitation on the high energy implanter and dose throughput at higher energies. The manufacturing of high performance (HP) homo-junction bipolar junction transistors (BJT) and hetero-junction bipolar transistors (HBT) and other similar structures requires the reduction of the vertical profile of the device as well as the reduction of transistor parasitics. In order to reduce the collector-to-emitter transit time of the carriers, it is preferable to position the sub-collector close to the collector-base junction. The benefits of collector doping profile reach a limit and, therefore, positioning the sub-collector close to the collector-base junction helps prevent the manufacture of a high breakdown (HB) device. However, no matter what selectively implanted collector profile is used, as the vertical profile is scaled, electric fields between the base and sub-collector increase, resulting in higher avalanche multiplication and eventually to a lower collector-emitter breakdown voltage (BVceo).
The sub-collector and “pedestal implants” are placed in a collector region to provide the reduction of the well-known Kirk effect. Heavily doped sub-collector regions are placed in transistor elements and the associated derivatives to provide reduction of the Kirk effect. Additionally, the “pedestal implant” is brought closer to the surface to provide a lessened Kirk effect to achieve a lower breakdown voltage and higher frequency device. This pedestal implant requires an additional implant process step and adds cost to a semiconductor process. To obtain a high breakdown (HB) transistor, there is no pedestal implant but a planar sub-collector region with a planar top and bottom surface. To provide a high performance (HP) transistor, the additional “pedestal implant” is placed above the sub-collector region to minimize the motion of the base-collector metallurgical junction during high current operation.
With the scaling of the vertical profile, implanted sub-collectors are utilized instead of the epitaxially formed sub-collector regions. Hence the vertical scaling of the sub-collector requires a lower dose implant in the sub-collector region. As the hot process is reduced, and shallower vertical profiles are archived, the sub-collector implant dose and energy must be reduced. This leads to higher collector sheet resistances, and lower unity power gain cutoff frequency (fMAX). Additionally, the narrower and lower dose sub-collector region leads to higher vertical injection into the substrate region. For heavily doped sub-collectors, the well-known Auger recombination is a dominant source of recombination in the collector region. Minority carrier recombination in the wide and heavily doped sub-collector regions minimize minority carrier injection to the collector-substrate region and into the semiconductor chip substrate. As a result, the scaling of the vertical profile leads to a higher injection into the substrate wafer, which can increase the noise in adjacent circuitry or elements.
The increase in the minority carrier injection into the substrate can also lead to latchup. Latchup occurs from formation of parasitic pnp element cross-couple with npn elements. Hence it is a motivation to minimize noise injection to prevent “external latchup” or “internal latchup” in a semiconductor chip.
The invention described below provides structures and methods to address these aforementioned issues.